• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
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  • 优先权
    • 专利摘要:
    Disclosed is a memory address data protection circuit, the circuit being adapted to: receive, on an input data bus (126), write data to be written to a memory device (104), and on an address bus (122), a corresponding write address; generate an address protection value based on the write address; and generating modified write data (WRITE DATA ') on an output data bus (128), the modified write data including the write data and the address protection value, the bus width of the data bus. output data (128) being larger than the width of the input data bus.
    公开号:FR3038752A1
    申请号:FR1556621
    申请日:2015-07-10
    公开日:2017-01-13
    发明作者:Eric Bernasconi；Richard O'connor
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING DATA
    ADDRESS
    Field
    The present disclosure relates to the field of memory interfaces, and in particular to a memory interface providing a method and circuit for protecting and verifying address data.
    Statement of Prior Art
    When writing to any type of memory device such as DRAM (Random Access Memory) or SRAM (Random Access Random Access Memory), it is possible for signals to pass through the input and / or output lines memory is damaged for example due to the occurrence of a single event.
    Although the memory interfaces often include a protection and / or correction mechanism for the data written and read from the memory, there is also a problem that the address data may be damaged. It is difficult to detect that the address data has been damaged, as this results in data being written or read at an incorrect address. The data stored at the wrong address may not be damaged, and so the protection mechanisms for the data signal will fail to identify / correct the error.
    Having damaged address data on the input / output lines of a memory can be considered relatively infrequent. However, for some applications, such as automotive applications, aviation, and / or space applications, it is desirable to obtain extremely reliable memory devices, since human security may depend on proper operation.
    There is therefore a need in the art for a method and device for protecting and verifying address data transmitted on the input / output lines of a memory. summary
    An object of embodiments of the present description is to at least partially meet one or more needs of the prior art.
    In one aspect, there is provided a circuit for protecting memory address data, the circuit being adapted to: receive, on an input data bus, write data to be written into a memory device, and on a bus address, a corresponding write address; generate an address protection value based on the write address; and generating modified write data on an output data bus, the modified write data including the write data and the address protection value, the output data bus width being larger than the output data bus; width of the input data bus.
    According to one embodiment, the circuit is further adapted to generate a data protection value based on the write data, the modified write data further comprising the data protection value.
    According to one embodiment, the circuit further comprises an address generation circuit adapted to generate a modified write address on an output address bus to the memory device.
    According to one embodiment, the address generating circuit is adapted to generate the modified write address by shifting the write address of a bit to the left.
    According to one embodiment, the number N of bits of the write data is less than the width M of the input data bus, and the address protection value is generated on the basis of a corresponding sub-address. at the position of the N bits of write data in the width of the address bus.
    According to one embodiment, the width M of the input data bus is equal to a multiple P of the number of bits N of the write data, the circuit comprising P address coders each of which is adapted to generate the value of address protection on the basis of a corresponding one of the sub-addresses.
    According to one embodiment, a protection data generation circuit is adapted to generate the address protection value by coding the write address to generate a value of Y bits, Y being smaller than the number of bits of 1 write address.
    According to one embodiment, the circuit further comprises an address range filter circuit adapted to determine whether the write address is in a range of addresses to be protected, the address protection value being generated only if the address is in the range of addresses to be protected.
    According to one embodiment, the circuit further comprises a bypass path for providing the write data directly to the write data output port if the write address is not in a range of addresses to protect, the bypass path comprising a bridging circuit adapted to convert N bits of write data to at least N + Y bits of write data.
    According to another aspect, a memory address data verification circuit is provided, the circuit being adapted to: receiving, on an address bus, a read address; generate an address protection value. reference based on the reading address; receiving, on a read data input bus from a memory device, read data and an address protection value read from the memory device; and checking the memory address data by comparing the address protection value read in the memory device with the reference address protection value.
    According to one embodiment, the number N of bits of the read data is less than the width M of a read data portion of the read data input bus, and the reference address protection value is generated on the basis of a subaddress corresponding to the position of the N bits of read data in the width of the read data portion of the read data input bus.
    According to one embodiment, the width M of the portion of read data of the read data input bus is equal to a multiple P of the number N of read data bits, the circuit comprising P address coders of which each is adapted to generate the address protection value on the basis of a corresponding one of the sub-addresses.
    In another aspect, there is provided an address protection / verification circuit comprising the aforementioned memory address data protection circuit and the aforementioned memory address data verification circuit.
    In yet another aspect, there is provided a method of protecting memory address data comprising: receiving, on an input data bus, write data to be written to a memory device and, on an address bus a corresponding write address; generate an address protection value based on the write address; and generating modified write data on an output data bus, the modified write data including the write data and the address protection value, the output data bus width being larger than the output data bus; width of the input data bus.
    In yet another aspect, there is provided a method of checking memory address data comprising: receiving, on an address bus, a read address; generating a reference address protection value based on the read address; receiving, on a read data input bus from a memory device, read data and an address protection value read from the memory device; and checking the memory address data by comparing the address protection value read in the memory device with the reference address protection value.
    Brief description of the drawings
    The foregoing and other features and advantages will be apparent from the following detailed description of embodiments, given by way of illustration and not limitation, with reference to the accompanying drawings, in which: FIG. schematically an integrated circuit in communication with a memory device according to an exemplary embodiment; FIG. 2 represents modified write data according to an exemplary embodiment; Fig. 3 is a flowchart illustrating operations in an address data protection method according to an exemplary embodiment; Figure 4 schematically illustrates a write address protection circuit of Figure 1 in more detail according to an exemplary embodiment; Fig. 5 is a flowchart illustrating operations in an address data verification method according to an exemplary embodiment of the present disclosure; and Figure 6 schematically illustrates an address verification circuit of Figure 1 in more detail according to an exemplary embodiment.
    detailed description
    FIG. 1 schematically represents an integrated circuit 102 and a memory device 104. The memory device 104 is for example a device with a DRAM or SRAM memory, or another type of addressable memory device. The memory device 104 is for example located outside the integrated circuit chip, which means that the input / output lines 106 between the integrated circuit 102 and the memory device 104 are in the form of wires and / or conductive tracks. In alternative embodiments, the memory device 104 could be integrated on the chip, as part of the integrated circuit 102.
    The integrated circuit 102 includes circuitry for interfacing with the memory device 104, and for example includes a physical interface layer 108, coupled to the input / output lines 106, a memory controller 110 coupled to the memory layer 104, physical interface 108, an address protection / verification circuit 112, a SoC (on-chip) interconnection 114, and a processing device 116. The processing device 116 is for example a CPU (central processing unit), a GPU (graphics processing unit), a DMA (direct memory access), etc.
    The processing device 116 is for example coupled to the memory controller 110 via a SoC interconnection 114, and via the protection / address verification circuit 112. However, in alternative embodiments, the circuit address protection / verification 112 could be incorporated in the memory controller 110 or in the processing device 116. An advantage of placing the circuit 112 between the processing device 116 and the memory controller 110 is that it is possible to use existing processing devices 116 and memory controllers 110, and that circuit 112 may be implemented such that it is transparent to existing circuits.
    The circuit 112 comprises, for example, an address protection circuit 118, and an address verification circuit 120.
    The address protection circuit 118 receives a write address (WRITE ADDR) on an input bus 122, the write address being for example provided to the address protection circuit on two paths. One of the paths is used to generate, on an output bus 124, a modified address to be provided to the memory device 104. The modified address has for example an extended address range. The other path is for example used to generate an address protection value based on the write address. The circuit 118 also receives write data (WRITE DATA) on an input bus 126, and supplies, on an output bus 128, the data to be written to the modified address in the memory device 104, which includes the write data and the address protection value.
    The address verification circuit 120 receives a read address (READ ADDR) on an input bus 130, the read address being for example supplied to the address verification circuit 120 on two paths. One of the paths is used to generate, on an output bus 132, a read read address to be supplied to the memory device 104. The modified address has for example an extended address range. The other path is for example used to generate a reference address protection value based on the read address. As a result of the read operation, the circuit 120 receives, on an input bus 134 from the memory device 104, the read data, which includes the address protection value that was written at the same time as the data. . The circuit 120 compares, for example, the address protection value read in the memory device 104 to the reference address protection value generated based on the read address. The circuit 120 provides read data (READ DATA) on an output bus 136, but this data is for example produced only if the address protection value matches the reference address protection value. Alternatively, the read data may still be produced, but a separate error signal (not shown in FIG. 1) may be activated on an output of the address verification circuit 120 to indicate that the address data has been damaged. This is because the address protection value read in the memory device will not match the reference address protection value if the write address has been corrupted and the data has been written by mistake in the memory address. address read, or if the address read was damaged, and an unwanted address was therefore read.
    Each address protection / verification circuit 112 may implement slicing so that the full width of the data bus is processed in smaller N-bit widths. For example, assuming that the data bus has a width of M bits, the data bus is for example processed in P slots of N bits, with M = PxN.
    Furthermore, as shown in FIG. 1, in some embodiments there may be a plurality of address protection / verification circuits operating in parallel, each circuit 112 being associated with a separate port of the memory controller 110.
    Figure 2 shows an example of the contents of the write data provided on the bus 128, to be written to a memory address of the memory device 104. The same content will also be read during a read operation.
    As illustrated, the write data comprises N system data bits (DATA), which correspond to the data provided by the processing device 116, to be written to the memory address. N is for example an integer equal to at least 4, and is for example a power of 2, greater than or equal to 8. In some embodiments, N is equal to the width M of the data input bus 126 of the circuit 118 of Figure 1. However, in alternative embodiments, one can advantageously obtain a more accurate address verification by taking N less than the width of the bus. For example, in some embodiments, the width of the bus 126 is 64 bit, and N is 8. More generally, N is for example equal to M / P, where P is an integer greater than or equal to 2.
    The write data, for example, also includes X bits forming a data protection value (DATA PROTECTION) and Y bits forming the address protection value (ADDRESS PROTECTION). The data protection value is optional, since in some embodiments the data protection is not implemented, or it is implemented by a different circuit, such as the memory controller 110.
    In some embodiments, X + Y = N, such that N + X + Y = 2N, where X is 0 or a positive integer, and Y is at least 1. The particular encoding mode used for generating the address protection value is for example selected on the basis of the available bits. For example, a single-bit address protection value is a simple parity check value. For example, there is an upper limit of Q, where Q is the number of bits of the address corresponding to the N-bit data. In such a case, the address is simply copied, without reducing the number of bits by a coding.
    In one embodiment, N is 8, X is 5, and Y is 3.
    FIG. 3 is a flowchart showing operations, implemented by the circuit 118, of an address data protection method according to an exemplary embodiment.
    In an operation 301, the circuit 118 receives N bits of data to be written to a memory device, and a corresponding write address.
    In a subsequent operation 302, circuit 118 generates a Y-bit address protection value, based on the write address. In some embodiments, a value derived from the write address is generated, and the address protection value is generated based on this derived value. For example, if the write data bus 126 is M bits, where M is equal to P times N, then P sub addresses are generated for example based on the write address, and a value of Different address protection is generated for each sub-address. The address protection value is, for example, any value for verifying the accuracy of the address data with at least some level of certainty. For example, the address protection value could include one or more parity check values, an error correction code such as a Hamming code, a cyclic redundancy check (CRC) code, or even a copy some or all of the address bits.
    In a subsequent operation 303, the write address range is for example increased to cover data blocks of at least N + Y bits. Indeed, the address provided on the address bus 122 is for example based on the blocks of N system data bits. Thus, the size of the address space is for example increased by the circuit 118 so that the address protection value can be stored in addition to the system data. For example, in the case where the width of the data bus is doubled, and assuming that the least significant bit (lsb) of the address corresponds to a byte, doubling the address will cause the address covers two bytes rather than a single byte. In alternative embodiments, however, it would be possible not to change the address, and instead, for each address it would be possible to cover a word that is twice as wide as each word provided on the data bus.
    In an operation 304, the N + Y bits are written to the modified write address in the memory device.
    Fig. 4 schematically illustrates the write address protection circuit 118 of Fig. 1 in more detail according to an exemplary embodiment.
    The input address bus (WRITE ADDR) 122 is for example coupled to an address range filter (ADDR RANG FILT) 402, which, for example, makes it possible to provide protection / address verification only at certain ranges of data. addresses in the memory device. For example, the memory device could be subdivided into a first portion for which protection / address verification should be provided, and another portion for which no protection / address verification should be provided.
    The output of circuit 402 is coupled to an address alignment circuit (ADDR ALIGN) 404, which for example increases the range of write addresses to allow the address protection value to be inserted, and optionally a data protection value. In a very simple example, the memory device may have an addressable range (expressed in hexadecimal) ranging from 0x00 to 0xFF, but the processing device 116 may only see an address range equal to only half of the total, for example. example the range of 0x00 to 0x7F. Thus, each of these addresses is for example converted into two adjacent physical addresses in the memory device, the 0x01 address becoming 0x02, the 0x02 address becoming 0x04, and so on, the 0x7F address becoming OxFE. These conversions correspond to a simple shift to the left of, a bit of each address. The modified write address WRITE ADDR 'is provided on the output address bus 124. The write address from the address filter 402 is also provided, for example, to a first-in, first-out buffer. (FIFO) 406, which for example stores one or more of the addresses, and provides them upon request to an address incrementing device (ADRR INC) 408, which is for example used to generate, on the basis of the address the addresses to be accessed during the write operation. The address incrementer 408 is for example adapted to increment the address by increments corresponding to the width of the write data bus 122. For example, if the write data bus 122 has a width of 8 bytes, and if the least significant bit of the address designates a byte, with each new block of write data on the write data bus 126, the address incrementing device 408 is for example adapted to increment the address in increments of 8.
    The output of the address incrementer 408 is provided to an address encoder (ADDR ENC) 410, which for example generates a Y-bit address protection value based on the address value, and provides the Y-bit value to a concatenation circuit 412. The address encoder 410, for example, generates the address protection value based on the address of the corresponding N-bit data value. In the case where the width M of the data bus is equal to N, the address encoder 410 will simply generate the address protection value based on the address provided by the address incrementer 408. However, if M is equal to PxN, where P is an integer greater than or equal to 2, the address encoder generates, for example, P different protection values, one for each block of N bits over the width of the data bus.
    For example, in the case where the data bus width is 2N, the address encoder 408 generates, for example, a first address protection value for the first N bits of the write data based on the address provided by the address incrementer 408, then generates a second address protection value for the N second bits of the write data on the basis of the address provided by the incrementing device. address 408, incremented by 1.
    The concatenation circuit 412 also receives the N system data bits supplied on the input write data bus 126. In the example of FIG. 4, the bus 126 is also coupled to a data encoder circuit 414 (FIG. DATA ENC), which for example encodes the data to generate an X-bit data protection value, also provided to the concatenation circuit 412.
    The circuit 412 concatenates the values of N, X and Y bits to form the write data to be written into the memory device. The output of the concatenation circuit 412 is for example coupled to an input of a multiplexer 416 which provides, on its output, write data (WRITE DATA ') on the data bus 128. Another input of the multiplexer 416 is for example, coupled to receive the write data from the input bus 126, without the addition of an address protection value or a data protection value. For example, the write data is provided through a bridging circuit (BRIDGE) 418, which converts N bits of write data provided on a single memory access cycle into 2N data bits. write on two memory access cycles. For example, on a first cycle, the N bits of write data are stored by the bridge 418, and on a subsequent cycle, when N other bits have been received, the 2N bits are provided on the bus 128. The multiplexer 416 is for example adapted to select the path passing through the bridge 418 if the write operation relates to a range of addresses which should not be added an address and data protection.
    In some embodiments, the address protection / verification circuit 112 performs slicing so that different portions of the data bus width are processed in parallel. In such a case, the address encoder 410, the concatenation circuit 412, and the data encoder 414 are each for example reproduced several times on the basis of the number of slices. The elements 410, 412, 414 of each slice for example process a corresponding block of N bits of the data bus. The instances of the address encoder 410, for example, each operate on a corresponding fixed offset of the address, representing the position of the N data bits in the width of the data bus. Further, in some embodiments, the granularity of read or write access is less than the data bus width, and is for example a multiplet, while the data bus has a width equal to one. plurality of multiplets. Thus, the read or write operation can point to a specific starting byte in the data bus width.
    To take a specific example, in one embodiment, M is 2N, and N is 8. There are for example 2 slots, which means that each of the address coder 410, the concatenation circuit 412 and data encoder 414 is reproduced twice. The following table gives examples of the consecutive addresses provided by the address incrementing device (ADDR INC) 408 and coded by the first of the address coders (ADDR ENC # 1) and by the second of the address coders ( ADDR ENC # 2) in such an embodiment:
    Fig. 5 is a flowchart illustrating operations in an address verification method according to an exemplary embodiment.
    In an operation 501, a read address is received.
    In a subsequent operation 502, the read address is processed to generate a Y-bit reference address protection value. The coding algorithm applied in
    operation 502 is the same as that applied in operation 302 of FIG.
    In a subsequent operation 503, the address range of the read access is increased to cover at least blocks of N + Y bits. This involves making the same change as described in connection with operation 303 of Figure 3, except that it is applied to a read address rather than a write address.
    In a subsequent operation 504, the memory access is realized, and the N + Y bits are read into the memory device.
    In a subsequent operation 505, the Y bit address protection value read in the memory circuit is compared to the reference address protection value. If it matches, for example, we consider that no damage has occurred in the address. On the other hand, if it does not match, an alert is generated, for example, and the read data can be eliminated.
    Figure 6 illustrates the address verification circuit 120 of Figure 1 in more detail according to an exemplary embodiment.
    As illustrated, the read address (READ ADDR) on the address path 130 is for example provided to an address range filter (ADDR RANGE FILT) 602, which is for example similar to the circuit 402 of the figure 4.
    The output of the address range filter 602 is for example supplied to an address alignment circuit (ADDR ALIGN) 604, which for example also operates in the same way as the circuit 404 of FIG. reading address range to cover both the system data and the corresponding address protection value. The circuit 604 provides the READ ADDR 'read address on the output address bus 132.
    The output of the address range filter 602 is, for example, supplied to a FIFO 606, which is coupled via a multiplexer (MUX) 608 to an address incrementing device (ADDR INC) 610. output of the address incrementer 610 is coupled to an address encoder (ADDR ENC) 612 which generates the reference address protection value (REF ADDR PROT) based on the read address. The address incrementer 610 and the address encoder 612 operate, for example, similarly to the address incrementer 408 and the address encoder 410.
    The multiplexer 608 is for example controlled by a READ DATA ID signal from the memory device 104, which for example indicates that they are the read data supplied on the bus 134, so that the multiplexer 608 selects the corresponding read address in FIFO 606. The address incrementing device 610 for example receives one or more phase tracking signals (PHASE TRACKING), and is used to ensure that the addresses generated by the incrementing device 610 correspond to the data read here. on the bus 134. In the case where the interface with the memory device is an AXI connection, said one or more phase tracking signals comprise, for example, RVALID, RREADY and RLAST signals, these signals being known to the human being. art.
    The circuit 120 also comprises a separator circuit 614, which receives, on the bus 134 coming from the memory device, the data read from the ADDR ADDR 'address, and which extracts the address protection value. This address protection value (ADDR PROT) is supplied to a comparator (COMPARE) 616, which also receives the reference address protection value from the address encoder 612. The comparator 616 compares the protection value of the address. address to the reference address protection value, and generates an error signal (ERROR) on an output line 618 of the comparator. If the address protection values match, the error signal is not activated. On the other hand, if there is a discrepancy between these values, the error signal is activated. In some embodiments, the line 618 is coupled to the processing device 116 providing the memory access, and the error signal indicates to the processing device 116 that the data read can not be relied on, since the signal address is damaged.
    In some embodiments, a data checking / correcting circuit (DATA CHECKING / CORRECTING) 620 is also provided, which receives from the separator circuit 614 the system data (DATA) extracted from the data read by the separator 614, and also the value X-bit data protection device (DATA PROT) retrieves data read by the separator 614. The output of the circuit 620 is for example coupled to a data multiplexer (DATA MCJX) 622, which supplies the data read on the output bus 136.
    The multiplexer 622 also receives the data read from the input bus 134 via a bridging circuit (BRIDGE) 624, which bypasses the circuits 614, 616 and 620 if the address of the read does not correspond to a protected address range. The bridging circuit 624 for example converts 2N bits of read data provided on a single memory access cycle into N data bits read over two memory access cycles. For example, on a first cycle, the 2N bits of data read from the bus 134 are stored by the bridge 624 and provided on the bus 136 over two cycles. The multiplexer 622 is for example adapted to select the path passing through the bridge 624 if the read operation relates to a range of addresses that did not receive the addition of an address and data protection.
    In some embodiments, slicing can be implemented in address verification circuit 120 in a manner similar to that previously described in connection with FIG. 4. In the embodiment of FIG. the elements 612, 614, 616 and 620 are for example duplicated so that each instance of these elements processes a block of N corresponding bits.
    An advantage of the embodiments described herein is that address protection is provided in a relatively simple manner, while maintaining a standard interface with the memory device. Indeed, the only modification is, for example, increasing the width of the data bus to the memory device, for example by doubling its width.
    With the description thus made of at least one illustrative embodiment, various alterations, modifications and improvements will readily occur to those skilled in the art.
    In particular, although examples have been described in which the sum of the X bits of the data protection value and the Y bits of the address protection value is equal to the number N of bits of the system data, many other formats would be possible. For example, it would be possible for X + Y to be equal to N / 2 or N / 4.
    权利要求:
    Claims (15)
    [1" id="c-fr-0001]
    A memory address data protection circuit, the circuit being adapted to receive, on an input data bus (126), write data to be written in a memory device (104), and on a address bus (122), a corresponding write address; generate an address protection value based on the write address; and generating modified write data (WRITE DATA ') on an output data bus (128), the modified write data including the write data and the address protection value, the bus width of the data bus. output data (128) being larger than the width of the input data bus.
    [2" id="c-fr-0002]
    The circuit of claim 1, wherein the circuit is further adapted to generate a data protection value based on the write data, the modified write data further comprising the data protection value.
    [3" id="c-fr-0003]
    The circuit of claim 1 or 2, further comprising an address generating circuit (404) adapted to generate a modified write address (WRITE ADDR ') on an output address bus (124) to the memory device.
    [4" id="c-fr-0004]
    The circuit of claim 3, wherein the address generation circuit (404) is adapted to generate the modified write address (WRITE ADDR ') by shifting the write address of a bit to the left.
    [5" id="c-fr-0005]
    The circuit of any one of claims 1 to 4, wherein the number N of bits of the write data is less than the width M of the input data bus (126), and the protection value of address is generated based on a subaddress corresponding to the position of the N bits of write data in the width of the address bus.
    [6" id="c-fr-0006]
    The circuit of any one of claims 1 to 5, wherein the width M of the input data bus (126) is equal to a multiple P of the number N of bits of the write data, the circuit comprising P address coders each of which is adapted to generate the address protection value on the basis of a corresponding one of the sub-addresses.
    [7" id="c-fr-0007]
    The circuit of any one of claims 1 to 6, wherein a protection data generation circuit (410) is adapted to generate the address protection value by encoding the write address to generate a value. Y bits, Y being smaller than the number of bits of the write address.
    [8" id="c-fr-0008]
    The circuit of any one of claims 1 to 7, further comprising an address range filtering circuit (402) adapted to determine whether the write address is in a range of addresses to be protected, in the address protection value is generated only if the address is in the range of addresses to be protected.
    [9" id="c-fr-0009]
    The circuit of claim 8, further comprising a bypass path for providing the write data directly to the write data output bus (128) if the write address is not within a range of addresses to be protected, the bypass path comprising a bridging circuit (418) adapted to convert N bits of write data to at least N + Y bits of write data.
    [10" id="c-fr-0010]
    10. A memory address data checking circuit, the circuit being adapted to: receiving, on an address bus (130), a read address; generating a reference address protection value (REF ADDR PROT) based on the read address; receiving, on a read data input bus (134) from a memory device (104), read data and an address protection value read from the memory device; and checking the memory address data by comparing the address protection value read in the memory device with the reference address protection value.
    [11" id="c-fr-0011]
    The circuit of claim 10, wherein the number N of bits of the read data is less than the width M of a read data portion of the read data input bus (134), and the value of reference address protection is generated based on a sub-address corresponding to the position of the N bits of read data in the width of the read data portion of the read data input bus (134) .
    [12" id="c-fr-0012]
    The circuit of claim 11, wherein the width M of the reading data bus read data portion (134) is equal to a multiple P of the number N of read data bits, the circuit comprising P address coders each of which is adapted to generate the address protection value on the basis of a corresponding one of the sub-addresses.
    [13" id="c-fr-0013]
    An address protection / verification circuit (112) comprising the circuit of any one of claims 1 to 9 and the circuit of any one of claims 10 to 12.
    [14" id="c-fr-0014]
    A method of protecting memory address data comprising: receiving, on an input data bus (126), write data to be written to a memory device (104) and, on an address bus ( 122), a corresponding write address; generate an address protection value based on the write address; and generating modified write data (WRITE DATA ') on an output data bus (128), the modified write data including the write data and the address protection value, the bus width of the data bus. output data (128) being larger than the width of the input data bus.
    [15" id="c-fr-0015]
    A method of verifying memory address data comprising: receiving, on an address bus (130), a read address; generating a reference address protection value (REF ADDR PROT) based on the read address; receiving, on a read data input bus (134) from a memory device (104), read data and an address protection value read from the memory device; and checking the memory address data by comparing the address protection value read in the memory device with the reference address protection value.
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    同族专利:
    公开号 | 公开日
    CN106340319A|2017-01-18|
    CN205692570U|2016-11-16|
    FR3038752B1|2018-07-27|
    CN106340319B|2020-05-12|
    US10248580B2|2019-04-02|
    US20170010980A1|2017-01-12|
    引用文献:
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    EP0674258A1|1994-03-24|1995-09-27|Texas Instruments France|Device for managing access conflict between a CPU and memories|
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    FR3038752B1|2015-07-10|2018-07-27|Stmicroelectronics Sas|METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING ADDRESS DATA|FR3038752B1|2015-07-10|2018-07-27|StmicroelectronicsSas|METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING ADDRESS DATA|
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    法律状态:
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    2017-01-13| PLSC| Search report ready|Effective date: 20170113 |
    2017-06-21| PLFP| Fee payment|Year of fee payment: 3 |
    2018-06-21| PLFP| Fee payment|Year of fee payment: 4 |
    2019-06-21| PLFP| Fee payment|Year of fee payment: 5 |
    2021-04-09| ST| Notification of lapse|Effective date: 20210305 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1556621|2015-07-10|
    FR1556621A|FR3038752B1|2015-07-10|2015-07-10|METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING ADDRESS DATA|FR1556621A| FR3038752B1|2015-07-10|2015-07-10|METHOD AND CIRCUIT FOR PROTECTING AND VERIFYING ADDRESS DATA|
    CN201620148491.9U| CN205692570U|2015-07-10|2016-02-26|For protecting the circuit with verifying memory address date and address protection/checking circuit|
    CN201610108842.8A| CN106340319B|2015-07-10|2016-02-26|Method and circuit for protecting and verifying address data|
    US15/055,896| US10248580B2|2015-07-10|2016-02-29|Method and circuit for protecting and verifying address data|
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